Ferroelectric random access memory (FRAM) devices are "nonvolatile" memory devices because they preserve data stored therein, even in the absence of a power supply signal. Each memory cell includes a capacitor composed of a ferroelectric material. The ferroelectric capacitor is composed of two conductive layers and a ferroelectric material layer formed therebetween. The ferroelectric materials used for the ferroelectric capacitor are typically Phase III potassium nitrate, bismuth titanate and lead zirconate titanate Pb(Zr, Ti)O.sub.3 (PZT). Ferroelectric materials have hysteresis characteristics. Thus, the polarity of the ferroelectric material can be maintained even after interruption of the power supply. Data (e.g., logic 0,1) is stored in the FRAM as the polarity state of the ferroelectric material in each capacitor.
The typical hysteresis characteristics of the ferroelectric material will be described in detail with reference to FIG. 1. In FIG. 1, the abscissa represents a voltage V applied across the electrodes of the ferroelectric capacitor, and the ordinate represents an amount of electric charge Q stored in the ferroelectric capacitor. The polarity-electric field (P-E) characteristics of the ferroelectric material is also similar to that of the Q-V characteristics shown in FIG. 1.
Due to the hysteresis characteristic of the ferroelectric capacitor, current passing through a capacitor is changed by the history of the voltage applied thereto. For example, assuming that the S4 state corresponds to data "1", the S1 state corresponds to data "0", the state of the ferroelectric capacitor is transferred from state S4 to state S5 and then to state S6 by application of a negative voltage. During this transfer, the electric charge amount Q.sub.R accumulated in the ferroelectric capacitor is changed to -Q.sub.R. At this time, a change of the accumulated charge becomes -2Q.sub.R, and accordingly a voltage of a bit line is changed as shown in formula (1): ##EQU1##
Here, C.sub.BL represents an equivalent capacitance of a bit line coupled to the ferroelectric capacitor.
However, in the event the ferroelectric capacitor is in the S1 state corresponding to data "zero", and then a negative voltage is applied, the S1 state is changed to the S6 state and the change in accumulated electric charge is slight. Thus, the change in potential of the bit line is negligible.
The hysteresis characteristic of the ferroelectric capacitor will now be described in more detail as follows. Assuming that an initial state of the ferroelectric capacitor is S1 in FIG. 1, if the voltage applied to the ferroelectric capacitor is increased, the state of the ferroelectric capacitor will transition from state S1 to state S2. The voltage applied to the ferroelectric capacitor in state S2 is typically referred to as the coercive voltage. If the intensity of the voltage applied to the ferroelectric capacitor is increased beyond the coercive voltage, the state of the ferroelectric capacitor will change from state S2 to state S3. In state S3, the ferroelectric capacitor has a first polarization which Is typically referred to as a positive polarization. As illustrated by FIG. 1, the removal of the positive voltage from a ferroelectric capacitor in state S3 will cause the capacitor to transition from state S3 to state S4, however, the first polarization state will be maintained. Finally, if the voltage applied to a ferroelectric capacitor in state S4 is made sufficiently negative, the state of the ferroelectric capacitor will transition to state S5 and then to state S6. In state S6, the ferroelectric capacitor has a second polarization which is typically referred to as a negative polarization. As illustrated by FIG. 1, the removal of the negative voltage from a ferroelectric capacitor In state S6 will cause the capacitor to transition from state S6 to state S1, however, the second polarization state will be maintained. As will be understood by those skilled in the art, a ferroelectric capacitor in the first and second polarization states is typically referred to as storing data "1" and data "0", respectively.
The polarization switching speed of a ferroelectric capacitor is approximately 10.sup.-9 sec, and the necessary program time of the ferroelectric capacitor is typically shorter than that of other nonvolatile memory devices such as electrically programmable read only memory (EPROM) devices, electrically erasable and programmable read only memory (EEPROM) devices and flash memory devices. As will be understood by those skilled in the art, the read/write cycle endurance of a ferroelectric capacitor is typically on the order of 10.sup.9 to 10.sup.12.
Conventional nonvolatile ferroelectric memory devices having ferroelectric capacitors will now be described with reference to FIGS. 2-4. In FIG. 2, a nonvolatile ferroelectric memory device includes nine memory cells. Each memory cell comprises one ferroelectric capacitor. The ferroelectric capacitor is connected between one of row lines R0, R1 and R2 and one of column lines C0, C1 and C2. A memory cell having the ferroelectric capacitor 101 is selected by applying a positive voltage, for example, 5 Volts, to the row line R0 and 0 Volts to the other row lines R1 and R2. At this time, the positive voltage is applied to upper conductive layers of the ferroelectric capacitors 102 and 103 as well as that of the ferroelectric capacitor 101. 0 Volts is applied to the column line C0. Accordingly, 5 Volts is applied across the ends of the selected ferroelectric capacitor 101, which causes the ferroelectric capacitor 101 to be in a first polarization state. At this time, 0 Volts is applied across the ferroelectric capacitor 104 so that the polarization state is not changed. However, a voltage of approximately 2.5 Volts is applied to the respective column lines C1 and C2 so that the voltages applied across the ferroelectric capacitors 102 and 103 should not change polarization states. After completion of a reading operation of the memory cell formed of the ferroelectric capacitor 101, an operation for restoring a state of initial polarization should be performed. Accordingly, 5 Volts is applied to the column line C0 and 0 Volts is applied to the row line R0. Also, 2.5 Volts is applied to the row lines R1 and R2 and 0 Volts is applied to the column lines C1 and C2. Accordingly, the nonvolatile ferroelectric memory device shown in FIG. 2 requires a driving circuit for generating a sequence of various combinational voltages. The driving circuit is complicated and may impede the high speed operation of the memory device. The driving circuit may also require a wide layout area.
FIG. 3 shows another conventional nonvolatile ferroelectric memory device, where a memory cell includes one access transistor and one ferroelectric capacitor. One memory cell is formed in correspondence to an intersection of each of the bit lines BL0, BL1, BL2, . . . , BLn with each of the word lines WL0, WL1, . . . , WLn. In a memory cell 110, a gate of an access transistor 111 is connected to the word line WL0, and a drain is connected to the bit line BL0. A ferroelectric capacitor 112 is connected between a source of the access transistor 111 and a plate line PL0. Plate lines PL0, PL1, . . . , PLn are alternately formed in parallel with the word lines WL0, WL1, . . . , WLn. A method for driving the nonvolatile ferroelectric memory device shown in FIG. 3 is disclosed in an article by T. Sumi, et al. entitled A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns, ISSCC Digest of Technical Papers, pp. 268-269, February (1994). In the nonvolatile ferroelectric memory device shown in FIG. 3, ferroelectric capacitors of all memory cells connected to a word line and plate line, as well as the memory cell on the word line and the plate line to be accessed during a reading/writing operation, are exposed to a fatigue cycle. Accordingly, the ferroelectric capacitors deteriorate. Also, a plate voltage is applied to all memory cells corresponding to the same word line during a reading/writing operation, to thereby consume a great deal of active power.
FIG. 4 shows still another conventional nonvolatile ferroelectric memory device, where one memory cell includes one access transistor and one ferroelectric capacitor. One memory cell is formed in correspondence to an intersection of each of the bit lines BL0, BL1, BL2, . . . , BLn with each of the word lines WL0, WL1, . . . , WLn. In the memory cell 120, a gate and a drain of an access transistor 121 are connected to the word line WL0 and the bit line BL0, respectively, and a source is connected to one end of a ferroelectric capacitor 122. Another end of the ferroelectric capacitor 122 is connected to a plate line PL0. Here, the plate lines PL0, PL1, . . . , PLn are alternately formed in parallel with the bit lines BL0, BL1 . . . BLn unlike in FIG. 3. A method for driving the nonvolatile ferroelectric memory device shown in FIG. 4, like in FIG. 3, is disclosed in the above Sumi et al. article. Unfortunately, the inclusion of the plate lines between alternating bit lines may impede the manufacturing process and reduce integration levels.